* New UART receive component with features similar to UART tx
* New UART simple testbench for the UART components
* TODO: checking of parity error
* Functional coverage
* Formal verification

* Add BMC mode to formal tests
* Adapt wishbone simulation testbench to new generics
* Integrate simulation PSL checks in Wishbone components
* Add generic for Simulation PSL checks to Wishbone components

* A lot of new checks are added to WishboneCheckerE unit
  trying to implement the rules of the Wishbone spec.
* An illegal use of the suffix implication instead of logical
  implicationis fixed in WishboneMasterE unit

* Add 1st initial version of WishBone checker unit
* Add Wishbone package with component & type declarations
* Replace WB slave register by dictionary

WB_WRITE & WB_READ check that a write/read transfer is started on the
WishBone bus if requested on the local port of the WishBoneMasterE unit
at the adequate time.

The second logical implication was made the whole property holding
when the part after the 1st implication didn't hold. So, the 2nd
implication is replaced by an and in combination with the next
operator. Now the property fails when one of the two and'ed parts after
the implication fails.

Various new PSL assertions to check ports during Wishbone write & read
transfer and reset state