* New UART receive component with features similar to UART tx
* New UART simple testbench for the UART components
* TODO: checking of parity error
* Functional coverage
* Formal verification

* A lot of new checks are added to WishboneCheckerE unit
  trying to implement the rules of the Wishbone spec.
* An illegal use of the suffix implication instead of logical
  implicationis fixed in WishboneMasterE unit

* Add 1st initial version of WishBone checker unit
* Add Wishbone package with component & type declarations
* Replace WB slave register by dictionary

Instead of using directed tests we switch to coverage driven ones
by using OSVVM capabilities.

A new stack implementation is added. It's a protected type t_stack,
included in the StackP package. It has the same methods like the
t_queue types but implements a stack logic instead of a queue one.
The t_stack type is tested in the StackT testbench.

Various new PSL assertions to check ports during Wishbone write & read
transfer and reset state