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14 Commits (0be16586c762fce192ac787f71e2e050a738108a)

Author SHA1 Message Date
  T. Meissner 0be16586c7 fixed ome bugs related to RNG integration; reg #1 & #2 are used to set the wait/run time of the RNG; reg #3 is RNG data register now 10 years ago
  T. Meissner 0e2170a504 add Fibonacci RNG and control unit; using register #0 as control/status and register #1 as data register for the RNG instance 10 years ago
  T. Meissner e64b387455 update constraint file to new design 10 years ago
  T. Meissner 943d8ca18d add clearing of SPIIRQ register 10 years ago
  T. Meissner a39d535248 add change of s_spi_frame to NOP after write/read cycle and no new preamble was received 10 years ago
  T. Meissner 91306866a9 fixed swapped clk & rst connections on WishBoneMasterE module 10 years ago
  T. Meissner 0614c3eefd Complete rework of RaspiFpgaCtrlE unit; 10 years ago
  T. Meissner f6dfbbcc01 add constraint file 10 years ago
  T. Meissner 6cd9accd03 changed spi ports sclk, miso & mosi to inout, so we can remove the internal helper signals 10 years ago
  T. Meissner a29b3119e9 minor bugfixes 10 years ago
  T. Meissner 1ca6188156 add WishBoneMasterE, OSC, RaspiFpgaCtrlE and EFB components 10 years ago
  T. Meissner ea35b8b595 add central control component of raspiFpga design 10 years ago
  T. Meissner 67c3c25ac4 add EFB configured as SPI slave 10 years ago
  T. Meissner 3fb359b26d initial commit of new project raspiFpga which uses the PIF FPGA board von bugblat 10 years ago