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cryptography ip-cores in vhdl / verilog
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cryptocores/ctraes/sim/vhdl/tb_ctraes.tcl

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CTR-AES: Fix counter incr & init; add 1st simple testbench * Fix counter init & increase enable to prevent aes_enc PSL assume error * Add CTR-AES testbench, at the moment without data checks
4 years ago
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  1. set signals [list]
  2. lappend signals "top.tb_ctraes.s_reset"
  3. lappend signals "top.tb_ctraes.s_clk"
  4. lappend signals "top.tb_ctraes.s_validin"
  5. lappend signals "top.tb_ctraes.s_acceptin"
  6. lappend signals "top.tb_ctraes.s_start"
  7. lappend signals "top.tb_ctraes.s_key"
  8. lappend signals "top.tb_ctraes.s_nonce"
  9. lappend signals "top.tb_ctraes.s_datain"
  10. lappend signals "top.tb_ctraes.s_validout"
  11. lappend signals "top.tb_ctraes.s_acceptout"
  12. lappend signals "top.tb_ctraes.s_dataout"
  13. set num_added [ gtkwave::addSignalsFromList $signals ]