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tmeissner
/
cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
222
Commits
1
Branch
1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
Tree:
3de7dd63a9
cryptocores
/
ctraes
/
sim
History
T. Meissner
b602931174
Fix CTR-init round, set of iv & key in 1st round only.
4 years ago
..
vhdl
Fix CTR-init round, set of iv & key in 1st round only.
4 years ago