cryptography ip-cores in vhdl / verilog
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  1. -- ======================================================================
  2. -- AES encryption/decryption
  3. -- Copyright (C) 2019 Torsten Meissner
  4. -------------------------------------------------------------------------
  5. -- This program is free software; you can redistribute it and/or modify
  6. -- it under the terms of the GNU General Public License as published by
  7. -- the Free Software Foundation; either version 2 of the License, or
  8. -- (at your option) any later version.
  9. -- This program is distributed in the hope that it will be useful,
  10. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. -- GNU General Public License for more details.
  13. -- You should have received a copy of the GNU General Public License
  14. -- along with this program; if not, write to the Free Software
  15. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  16. -- ======================================================================
  17. library ieee;
  18. use ieee.std_logic_1164.all;
  19. use ieee.numeric_std.all;
  20. use work.aes_pkg.all;
  21. entity aes_enc is
  22. generic (
  23. design_type : string := "ITER"
  24. );
  25. port (
  26. reset_i : in std_logic; -- async reset
  27. clk_i : in std_logic; -- clock
  28. key_i : in std_logic_vector(0 to 127); -- key input
  29. data_i : in std_logic_vector(0 to 127); -- data input
  30. valid_i : in std_logic; -- input key/data valid flag
  31. accept_o : out std_logic;
  32. data_o : out std_logic_vector(0 to 127); -- data output
  33. valid_o : out std_logic; -- output data valid flag
  34. accept_i : in std_logic
  35. );
  36. end entity aes_enc;
  37. architecture rtl of aes_enc is
  38. begin
  39. IterG : if design_type = "ITER" generate
  40. signal s_round : t_enc_rounds;
  41. begin
  42. CryptP : process (reset_i, clk_i) is
  43. variable v_state : t_datatable2d;
  44. variable v_key : t_key;
  45. begin
  46. if (reset_i = '0') then
  47. v_state := (others => (others => (others => '0')));
  48. v_key := (others => (others => '0'));
  49. s_round <= 0;
  50. accept_o <= '0';
  51. data_o <= (others => '0');
  52. valid_o <= '0';
  53. elsif (rising_edge(clk_i)) then
  54. case s_round is
  55. when 0 =>
  56. accept_o <= '1';
  57. if (accept_o = '1' and valid_i = '1') then
  58. accept_o <= '0';
  59. v_state := set_state(data_i);
  60. v_key := set_key(key_i);
  61. s_round <= s_round + 1;
  62. end if;
  63. when 1 =>
  64. v_state := addroundkey(v_state, v_key);
  65. v_key := key_round(v_key, s_round-1);
  66. s_round <= s_round + 1;
  67. when t_enc_rounds'high-1 =>
  68. v_state := subbytes(v_state);
  69. v_state := shiftrow(v_state);
  70. v_state := addroundkey(v_state, v_key);
  71. s_round <= s_round + 1;
  72. -- set data & valid to save one cycle
  73. valid_o <= '1';
  74. data_o <= get_state(v_state);
  75. when t_enc_rounds'high =>
  76. if (valid_o = '1' and accept_i = '1') then
  77. valid_o <= '0';
  78. data_o <= (others => '0');
  79. s_round <= 0;
  80. -- Set accept to save one cycle
  81. accept_o <= '1';
  82. end if;
  83. when others =>
  84. v_state := subbytes(v_state);
  85. v_state := shiftrow(v_state);
  86. v_state := mixcolumns(v_state);
  87. v_state := addroundkey(v_state, v_key);
  88. v_key := key_round(v_key, s_round-1);
  89. s_round <= s_round + 1;
  90. end case;
  91. end if;
  92. end process CryptP;
  93. psl : block is
  94. signal s_key , s_din, s_dout : std_logic_vector(0 to 127) := (others => '0');
  95. begin
  96. process (clk_i) is
  97. begin
  98. if (rising_edge(clk_i)) then
  99. s_key <= key_i;
  100. s_din <= data_i;
  101. s_dout <= data_o;
  102. end if;
  103. end process;
  104. default clock is rising_edge(clk_i);
  105. -- initial reset
  106. restrict {not reset_i; reset_i[+]}[*1];
  107. -- constraints
  108. assume always (valid_i and not accept_o -> next valid_i);
  109. assume always (valid_i and not accept_o -> next key_i = s_key);
  110. assume always (valid_i and not accept_o -> next data_i = s_din);
  111. ACCEPTO_c : cover {accept_o};
  112. ACCEPT_IN_ROUND_0_ONLY_a : assert always (accept_o -> s_round = 0);
  113. VALIDI_AND_ACCEPTO_c : cover {valid_i and accept_o};
  114. ACCEPT_OFF_WHEN_VALID_a : assert always (valid_i and accept_o -> next not accept_o);
  115. VALIDO_c : cover {valid_o};
  116. VALID_IN_LAST_ROUND_ONLY_a : assert always (valid_o -> s_round = t_enc_rounds'high);
  117. VALIDO_AND_ACCEPTI_c : cover {valid_o and accept_i};
  118. VALID_OFF_WHEN_ACCEPTED_a : assert always (valid_o and accept_i -> next not valid_o);
  119. VALIDO_AND_NOT_ACCEPTI_c : cover {valid_o and not accept_i};
  120. VALID_STABLE_WHEN_NOT_ACCEPTED_a : assert always (valid_o and not accept_i -> next valid_o);
  121. DATA_STABLE_WHEN_NOT_ACCEPTED_a : assert always (valid_o and not accept_i -> next data_o = s_dout);
  122. end block psl;
  123. end generate IterG;
  124. end architecture rtl;