T. Meissner
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5640e7884b
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Update CBCDES unit and tests
* Use des from des dir instead of local copies
* Adapt testbench to des interface
* Add Makefile for VHDL-synthesis
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4 years ago |
T. Meissner
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716ce2725b
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moved array type definitions out of functions to head of package, instances now also in package head and are constants
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11 years ago |
T. Meissner
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f76ae71dd3
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beauty care
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12 years ago |
T. Meissner
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4489748aec
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initial commit os CBCDES verilog design file
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12 years ago |
T. Meissner
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c42beff5b8
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moved vhdl design files in directory 'vhdl'
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12 years ago |
T. Meissner
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ab47fd3a54
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import verilog des design files from des project
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12 years ago |
T. Meissner
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6356f624af
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moved vhdl design files in directory 'vhdl'
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12 years ago |
Torsten Meissner
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4b8ab0d0cc
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added async reset to des-module to avoid simulation warnings and unititialized ports
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13 years ago |
Torsten Meissner
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5f440e10ad
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Revision 0.2 2011/10/06
corrected some bugs which were found while testing cbc ability
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13 years ago |
Torsten Meissner
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b9ed938d6d
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register mode_i and iv_i only if start_i is high
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13 years ago |
Torsten Meissner
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5c4b112411
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Initial Release of CBC-DES
cbcdes.vhd and tb_cbcdes.vhd are still incomplete, maybe they contain
some bugs
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13 years ago |