T. Meissner
5c74abc86f
added wait for disactivated reset before running testcases
10 years ago
T. Meissner
5fff1d89d1
initial commit of verilog simulation environment for tdes core
12 years ago
T. Meissner
734efbc59f
added test cases for decryption in stimuli & checker; bugfix wwith validout detection
12 years ago
T. Meissner
fd799eeed1
change in error message
12 years ago
T. Meissner
9a340f5524
added timescale directive and set it to 1 ns/1 ps
12 years ago
T. Meissner
e40682386a
testbench enhancement
* now 2 files with stimuli data: data_input.txt & key_input.txt
* new file with the expetcted data output: data_output.txt
* new test: Inverse permutation known answer test
12 years ago
Torsten Meissner
9a29954670
new stimuli, checker & reset processes
13 years ago
Torsten Meissner
8f2e24fb8c
new verilog testbench, makefile & tcl-file
13 years ago
Torsten Meissner
804a359af4
new synchronous process for mode & valid signals
13 years ago
Torsten Meissner
c1f59849e5
initial release of des function package in verilog
13 years ago
Torsten Meissner
93186c5d1c
initial release of des verilog implementation, framework code only at the moment
13 years ago
Torsten Meissner
78db757f9d
new verily version of ads, startup code only at the moment
13 years ago