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cryptocores
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2 Commits (f8226943a33f8d990814506ed0e37bcbc058f8ad)

Author SHA1 Message Date
  T. Meissner f8226943a3 changed reset & clk timing according to vhdl testbench 11 years ago
  T. Meissner e62c0d5916 added verilog simulation environment 11 years ago
  T. Meissner 5fff1d89d1 initial commit of verilog simulation environment for tdes core 11 years ago
  T. Meissner 734efbc59f added test cases for decryption in stimuli & checker; bugfix wwith validout detection 11 years ago
  T. Meissner fd799eeed1 change in error message 11 years ago
  T. Meissner 9a340f5524 added timescale directive and set it to 1 ns/1 ps 11 years ago
  T. Meissner e40682386a testbench enhancement 11 years ago
  Torsten Meissner 9a29954670 new stimuli, checker & reset processes 12 years ago
  Torsten Meissner 8f2e24fb8c new verilog testbench, makefile & tcl-file 12 years ago
  Torsten Meissner 804a359af4 new synchronous process for mode & valid signals 12 years ago
  Torsten Meissner c1f59849e5 initial release of des function package in verilog 12 years ago
  Torsten Meissner 93186c5d1c initial release of des verilog implementation, framework code only at the moment 12 years ago
  Torsten Meissner 78db757f9d new verily version of ads, startup code only at the moment 12 years ago