cryptography ip-cores in vhdl / verilog

vhdl ghdl osvvm fpga testbenches verilog cryptography

T. Meissner 735c411ff8 First working version of AES enc & dec * Split enc & dec in separate units aes_enc & aes_dec * Add component declarations to aes_pkg * Key schedule isn't implemented yet * Fixed round keys at the moment until key schedule is implemented * Simple test of enc & dec * New aes top level unit (empty at the moment) * Renamed makefile to Makefile		5 years ago
aes	First working version of AES enc & dec	5 years ago
cbcdes	moved array type definitions out of functions to head of package, instances now also in package head and are constants	10 years ago
cbcmac_des	merge last changes from amc mini repo	9 years ago
cbctdes	removed internal synced copy of reset_i; set ready to high in reset	10 years ago
des	merge last changes from amc mini repo	9 years ago
tdes	added removing of tb_tdes binary and *.o files in clean target	10 years ago
.gitignore	added ignore file	10 years ago
LICENSE.textile	added GPLv2 license file	9 years ago
README.md	Created Readme.md file	7 years ago

README.md

cryptocores

cryptography ip-cores in vhdl / verilog

The components in this repository are not intended for productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.