cryptography ip-cores in vhdl / verilog
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
umarcor 7835fc5204 readme: use shield/badge from shields.io 2 years ago
.github ci: rename 'test' workflow to 'Simulation' 2 years ago
aes aes: fix build arg order 2 years ago
cbcdes Update CBCDES unit and tests 2 years ago
cbcmac_aes Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 2 years ago
cbcmac_des Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 2 years ago
cbctdes Add Makefile for synthesis of CBCTDES 2 years ago
ctraes CTR-AES: Fix counter incr & init; add 1st simple testbench 2 years ago
des Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 2 years ago
lib Add OSVVM as submodule 2 years ago
tdes Minor update to TDES sim makefile and testbench 2 years ago
.gitignore added ignore file 9 years ago
.gitmodules Add OSVVM as submodule 2 years ago
LICENSE.textile added GPLv2 license file 8 years ago
README.md readme: use shield/badge from shields.io 2 years ago

README.md

'simulation' workflow Status

cryptocores

Cryptography IP-cores & tests written in VHDL / Verilog

The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.

HINT:

The tests of some algorithms use the OSVVM library, which is redistributed as submodule. To get & initialize the submodule, please use the --recursive option when cloning this repository.