tmeissner
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formal_hw_verification
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7 Commits (master)

Author SHA1 Message Date
  T. Meissner 3d57fff226 Replace reset checks by async VHDL asserts; Add assumptions about inputs 3 years ago
  T. Meissner f2f433b165 Use PSL functions instead of workarounds; add forgotten always to asserts in alu 4 years ago
  T. Meissner 3e621b02e9 Add alu checks 4 years ago
  T. Meissner d420b00310 Making alu design work with GHDL synthesis 4 years ago
  T. Meissner ac767bb9d3 Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 5 years ago
  T. Meissner 7aa4aa52a8 Data in/put width now unconstrained 5 years ago
  T. Meissner 4feec0fff6 Inital commit 6 years ago