tmeissner
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gatemate_experiments
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4 Commits (main)

Author SHA1 Message Date
  T. Meissner 5d9943c78f Remove CC_CTRL_END component, use CC_USR_RSTN instead 1 year ago
  T. Meissner 6b1b376932 Use speed instead of moderate FPGA speed grade 2 years ago
  T. Meissner 32fa71a90b Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 2 years ago