tmeissner
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gatemate_experiments
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7 Commits (3b6a315a0d399e6ab213eac43755d5fa6413f1aa)

Author SHA1 Message Date
  T. Meissner 3b6a315a0d Add user_components.vhd containing generic RTL modules 3 years ago
  T. Meissner 6cffeef4a5 Rename components.vhd to rtl_components.vhd 3 years ago
  T. Meissner a0fcc51dc8 Add make target to program FPGA 3 years ago
  T. Meissner f28d35d12b Also remove bit file in clean target 3 years ago
  T. Meissner efaca0c912 Add PnR pass and constraint file 3 years ago
  T. Meissner 95887cb31d Add PLL to blink design 3 years ago
  T. Meissner 45ced01c22 Add blink design & simulation 3 years ago