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gatemate_experiments
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20 Commits (3b6a315a0d399e6ab213eac43755d5fa6413f1aa)
 

Author SHA1 Message Date
  T. Meissner 3b6a315a0d Add user_components.vhd containing generic RTL modules 2 years ago
  T. Meissner 6cffeef4a5 Rename components.vhd to rtl_components.vhd 2 years ago
  T. Meissner 61affc8b49 Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 2 years ago
  T. Meissner 0e84416a92 Rename uart folder to uart_reg 2 years ago
  T. Meissner 1003634110 Add inital version of uart register test design 2 years ago
  T. Meissner cfa6f88c55 Add simple gatemate primitives simulation components 2 years ago
  T. Meissner 012de1f868 RTL refactoring 2 years ago
  T. Meissner d57f683506 Adapt sim to updated RTL 2 years ago
  T. Meissner 133e25aa3d Let LEDs rotate instead of counting up 2 years ago
  T. Meissner a0fcc51dc8 Add make target to program FPGA 2 years ago
  T. Meissner eb0d52e2d6 Add blink design info and more links to README 2 years ago
  T. Meissner 81be6cfd05 Add CC_CFG_END unit, Use PLL lock & cfg_end for reset 2 years ago
  T. Meissner f28d35d12b Also remove bit file in clean target 2 years ago
  T. Meissner efaca0c912 Add PnR pass and constraint file 2 years ago
  T. Meissner 95887cb31d Add PLL to blink design 2 years ago
  T. Meissner 45ced01c22 Add blink design & simulation 2 years ago
  T. Meissner a38eedb326 Add license 2 years ago
  T. Meissner eea3893d1c Fix readme 2 years ago
  T. Meissner e60d14ba47 Add readme 2 years ago
  T. Meissner b8d8b791dc Initial commit 2 years ago