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gatemate_experiments
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1 Commits (f8ba0b17c2f836a72a259a300ffc321c283f4800)

Author SHA1 Message Date
  T. Meissner f8ba0b17c2 Add VHDL sim for RTL & Verilog sim for post-syn simulation 2 years ago
  T. Meissner b8d7ecd701 Update neorv32_aes top level; Add some iverilog options 2 years ago
  T. Meissner b01669c135 Update Makefile to build cryptocores AES-CTR component 2 years ago
  T. Meissner dc0e1aa90f Update top-level & Makefile to use new AES CF module 2 years ago
  T. Meissner 99971e7299 We have a config with uart which gatemate p_r-tool can handle 2 years ago
  T. Meissner 4cc4aa25e2 Add neorv32_aes design 2 years ago