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gatemate_experiments/uart_loop
T. Meissner 5d9943c78f Remove CC_CTRL_END component, use CC_USR_RSTN instead 1 year ago
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rtl Remove CC_CTRL_END component, use CC_USR_RSTN instead 1 year ago
sim Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
syn Use speed instead of moderate FPGA speed grade 2 years ago