Examples and design pattern for VHDL verification

vhdl ghdl osvvm psl fpga testbenches coverage

T. Meissner 52f45b24bf Add LGPL3 license file		9 years ago
osvvm_fsm_coverage	Fixed assert error by adding reset in assert precondition	9 years ago
psl_endpoint_eval_in_vhdl	Add writing psl endpoint value into VHDL boolean signal	9 years ago
psl_test_endpoint	Adapt to new GHDL feature to make endpoints visible in VHDL	9 years ago
LICENSE.md	Add LGPL3 license file	9 years ago
README.md	Add README.md	9 years ago

README.md

vhdl_verification

Examples and design pattern for VHDL verification. All examples run with GHDL, the open source VHDL simulator. You have to use the latest version of GHDL, as the examples use features which where added to GHDL very recently.

osvvm_fsm_coverage

Example to use OSVVMs CoveragePkg package to do FSM state coverage. State changes are used as BINS which are counted in an object of type CovPType. The testbench accesses these state coverage data CoveragePkg procedures. So, the testbench can react to the FSM coverage if necessary. Furthermore the state changes are checked by some PSL assertions.

psl_endpoint_eval_in_vhdl

Example to show a recently feature added to GHDL which allows to evaluate PSL endpoints in VHDL code. It simply defines an PSL endpoint and sets a boolean value dependent on the value of the PSL endpoint.

psl_test_endpoint

This example was as test case to check the feature of evaluating PSL endpoints in VHDL, which was recently added to GHDL. See GHDL issue #45 for details.