cryptography ip-cores in vhdl / verilog
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11 years ago
11 years ago
  1. -- ======================================================================
  2. -- AES encryption/decryption
  3. -- algorithm according to FIPS 197 specification
  4. -- Copyright (C) 2020 Torsten Meissner
  5. -------------------------------------------------------------------------
  6. -- This program is free software; you can redistribute it and/or modify
  7. -- it under the terms of the GNU General Public License as published by
  8. -- the Free Software Foundation; either version 2 of the License, or
  9. -- (at your option) any later version.
  10. -- This program is distributed in the hope that it will be useful,
  11. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. -- GNU General Public License for more details.
  14. -- You should have received a copy of the GNU General Public License
  15. -- along with this program; if not, write to the Free Software
  16. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. -- ======================================================================
  18. library ieee;
  19. use ieee.std_logic_1164.all;
  20. use ieee.numeric_std.all;
  21. use work.aes_pkg.all;
  22. entity aes is
  23. generic (
  24. design_type : string := "ITER"
  25. );
  26. port (
  27. reset_i : in std_logic; -- async reset
  28. clk_i : in std_logic; -- clock
  29. mode_i : in std_logic; -- mode: 0 = encrypt, 1 = decrypt
  30. key_i : in std_logic_vector(0 to 127); -- key input
  31. data_i : in std_logic_vector(0 to 127); -- data input
  32. valid_i : in std_logic; -- input key/data valid flag
  33. accept_o : out std_logic;
  34. data_o : out std_logic_vector(0 to 127); -- data output
  35. valid_o : out std_logic; -- output data valid flag
  36. accept_i : in std_logic
  37. );
  38. end entity aes;
  39. architecture rtl of aes is
  40. signal s_mode : std_logic;
  41. signal s_accept_enc : std_logic;
  42. signal s_valid_enc : std_logic;
  43. signal s_data_enc : std_logic_vector(data_o'range);
  44. signal s_accept_dec : std_logic;
  45. signal s_valid_dec : std_logic;
  46. signal s_data_dec : std_logic_vector(data_o'range);
  47. begin
  48. inputregister : process (clk_i, reset_i) is
  49. begin
  50. if (reset_i = '0') then
  51. s_mode <= '0';
  52. elsif(rising_edge(clk_i)) then
  53. if (valid_i = '1' and accept_o = '1') then
  54. s_mode <= mode_i;
  55. end if;
  56. end if;
  57. end process inputregister;
  58. accept_o <= s_accept_enc and s_accept_dec;
  59. data_o <= s_data_enc when s_mode = '0' else s_data_dec;
  60. valid_o <= s_valid_enc when s_mode = '0' else s_valid_dec;
  61. i_aes_enc : entity work.aes_enc
  62. generic map (
  63. design_type => design_type
  64. )
  65. port map (
  66. reset_i => reset_i,
  67. clk_i => clk_i,
  68. key_i => key_i,
  69. data_i => data_i,
  70. valid_i => valid_i and not mode_i,
  71. accept_o => s_accept_enc,
  72. data_o => s_data_enc,
  73. valid_o => s_valid_enc,
  74. accept_i => accept_i
  75. );
  76. i_aes_dec : entity work.aes_dec
  77. generic map (
  78. design_type => design_type
  79. )
  80. port map (
  81. reset_i => reset_i,
  82. clk_i => clk_i,
  83. key_i => key_i,
  84. data_i => data_i,
  85. valid_i => valid_i and mode_i,
  86. accept_o => s_accept_dec,
  87. data_o => s_data_dec,
  88. valid_o => s_valid_dec,
  89. accept_i => accept_i
  90. );
  91. end architecture rtl;