cryptocores

1.7 MiB

Author	SHA1	Message	Date
T. Meissner	a2c530928e	Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring	4 years ago
T. Meissner	735c411ff8	First working version of AES enc & dec * Split enc & dec in separate units aes_enc & aes_dec * Add component declarations to aes_pkg * Key schedule isn't implemented yet * Fixed round keys at the moment until key schedule is implemented * Simple test of enc & dec * New aes top level unit (empty at the moment) * Renamed makefile to Makefile	6 years ago
T. Meissner	42a5eb9b1b	Minor refactoring & bugfixing * Set VHDL standard to VHDL 2008 * Replace rcon() functuion by simple array constant * Correct loop range in addroundkey() function	6 years ago
T. Meissner	2f91130184	Add remaining AES functions * addroundkey() * subword() * rotword() * rcon()	9 years ago
T. Meissner	8a7e15763a	beauty care	11 years ago
Torsten Meissner	6737c9bf49	partition design in ovl and not ovl enabled new generic in aes.vhd: ovl_enable (boolean); copy of aes_pkg.vhd to integrate ovl functions; copy of tb_aes.vhd to integrate ovl function	13 years ago
Torsten Meissner	2e948cf1aa	divide rtl directory in 2 sub-directories: vhdl & verilog move all rtl *.vhd files into the new vhdl directory in the rtl directory	13 years ago
Torsten Meissner	42d69ab72f	Initial release, pre-alpha state, only framework code	13 years ago