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cryptography ip-cores in vhdl / verilog
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cryptocores/tdes/sim
T. Meissner 2d708cbb51 Minor update to TDES sim makefile and testbench 3 years ago
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verilog added wait for disactivated reset before running testcases 10 years ago
vhdl Minor update to TDES sim makefile and testbench 3 years ago