WB_WRITE & WB_READ check that a write/read transfer is started on the
WishBone bus if requested on the local port of the WishBoneMasterE unit
at the adequate time.
The new checker monitor WishBoneBusMonitorP checks that address & data
on the WishBone bus are equal to the ones wihich were given at the local
port of the WishBoneMasterE unit to initiate the transfer.
The second logical implication was made the whole property holding
when the part after the 1st implication didn't hold. So, the 2nd
implication is replaced by an and in combination with the next
operator. Now the property fails when one of the two and'ed parts after
the implication fails.
New functions added:
* count_ones(): returns number of 1 in a given std_logic_vector
* xor_reduce(): returns the xor of all bits in a std_logic_vector
Functions even_parity() & odd_parity() now use the xor_reduce function
to calc the parity.
New testcases for checking correctness of removing and overwriting
entries in dictionary. Furthermore the hasKey() method is tested and
the clearing of the dictionary with the clear() method
In procedure was a bug regarding the test of the position of the
founded key/value pair. Because of this bug, a segmentation fault
happened when deallocationg the key/value pair. This is fixed now by
checking both neighbor entries for null
A new packae DictP.vhd is added which contains a simple implementation
of a dictionary type. It consists of a protected type t_dict which
contains procedures & functions which serve as methods to interact with
the protected type. The t_dict type is realised by a (double)
linked-list using access types.
The key type is string of arbitrary size, the data type is
std_logic_vector of arbitrary size. The t_dict type provides following
interface methods:
* set: set a key/value pair
* get: get a key/value pair
* del: remove a key/value pair
* init: initialise the dictionary
* clear: remove all key/value pairs
* hasKey: check if a key exists in the dictionary
* size: get number of key/value pairs
By using an actual version of GHDL, we don't need the VHDL-08
proposal libraries anymore. Enough features of VHDL-08 are integrated
in GHDL to compile OSVVM and our testbenches
The new common folder holds packages and designs, which can be used
either for synthesis & simulation. The first file is UtilP.vhd, a
package containing vatious helper functions:
* and_reduce(): function to and'ring all items of a vector, overloaded
for std_logic_vector & boolean_vector
* or_reduce(): function to or'ring all items of a vector, overloaded
for std_logic_vector & boolean_vector
* even_parity(): calculate the even parity of a std_logic_vector
* odd_parity(): calculate the odd parity of a std_logic_vector
By using an std_logic_vector access type for the data field in the
queue record, we cann now push data with any arbitrary length in the
t_queue object. Mixed lengths are also possible now :)
