By using an actual version of GHDL, we don't need the VHDL-08
proposal libraries anymore. Enough features of VHDL-08 are integrated
in GHDL to compile OSVVM and our testbenches

The new common folder holds packages and designs, which can be used
either for synthesis & simulation. The first file is UtilP.vhd, a
package containing vatious helper functions:

  * and_reduce(): function to and'ring all items of a vector, overloaded
                  for std_logic_vector & boolean_vector
  * or_reduce(): function to or'ring all items of a vector, overloaded
                 for std_logic_vector & boolean_vector
  * even_parity(): calculate the even parity of a std_logic_vector
  * odd_parity(): calculate the odd parity of a std_logic_vector

By using an std_logic_vector access type for the data field in the
queue record, we cann now push data with any arbitrary length in the
t_queue object. Mixed lengths are also possible now :)