* New UART receive component with features similar to UART tx
* New UART simple testbench for the UART components
* TODO: checking of parity error
* Functional coverage
* Formal verification

ci: add GitHub Actions 'test' workflow

* Add BMC mode to formal tests
* Adapt wishbone simulation testbench to new generics
* Integrate simulation PSL checks in Wishbone components
* Add generic for Simulation PSL checks to Wishbone components

* A lot of new checks are added to WishboneCheckerE unit
  trying to implement the rules of the Wishbone spec.
* An illegal use of the suffix implication instead of logical
  implicationis fixed in WishboneMasterE unit

* Add 1st initial version of WishBone checker unit
* Add Wishbone package with component & type declarations
* Replace WB slave register by dictionary

Typofix

Better use OSVVMs Alert package instead of AssertP routines

* New test case of local write & read at same time
* Add check for WB cycle dependent of WB master local write & read

Instead of using directed tests we switch to coverage driven ones
by using OSVVM capabilities.

The new setIter() procedure replaces the setFirst/setLast procedures
by implementing both versions. A new datatype t_dict_iter is added which
serves as parameter type for the setFirst() procedure.