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cryptocores
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15 Commits (2a3fae594fbe3b841cdc60b237a178322a2ced0d)

Author SHA1 Message Date
  T. Meissner 2d708cbb51 Minor update to TDES sim makefile and testbench 4 years ago
  T. Meissner a2c530928e Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 years ago
  T. Meissner 1d858ce952 added removing of tb_tdes binary and *.o files in clean target 11 years ago
  T. Meissner dafb56c966 added wait for disactivated reset before running testcases 11 years ago
  T. Meissner 5c74abc86f added wait for disactivated reset before running testcases 11 years ago
  T. Meissner 5fff1d89d1 initial commit of verilog simulation environment for tdes core 12 years ago
  T. Meissner dd979b5cd3 adapt makefile to new directory structure; new variable SRC_FILES for vhdl sources 12 years ago
  T. Meissner 715b8b1229 beauty care 12 years ago
  T. Meissner 30a7af4830 moved into seperate vhdl folder 12 years ago
  T. Meissner 5e422923cf moved into seperate vhdl folder 12 years ago
  Torsten Meissner 114a4e1072 remove OVL support in older, finished & verified projects 13 years ago
  Torsten Meissner 8fd02d0844 you can now include the OVL library if you set the OVL_ENABLE flag to 1 13 years ago
  Torsten Meissner c5fa11fbef integrated tcl-file into gtkwave starting parameters 13 years ago
  Torsten Meissner d3314a7d46 minor updates 13 years ago
  Torsten Meissner a288199209 initial release of testbench and makefile 13 years ago