tmeissner
/
libvhdl
1
0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Activity
68 Commits
2 Branches
914 KiB
Tree: 41f76efd9b
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '41f76efd9b'
${ noResults }
Commit Graph

68 Commits (41f76efd9b11d152c1cd3c22f7a9428f3d52278a)
 

Author SHA1 Message Date
  T. Meissner 41f76efd9b Switched to OSVVM 2014.01 9 years ago
  T. Meissner 6d57c594ed Queue can store data with type slv with arbitrary length 9 years ago
  T. Meissner 1bb058f3a2 Changed to OHDL license 9 years ago
  T. Meissner 9761e5660e Changed from LGPLv3 to OHDL license 9 years ago
  T. Meissner 4c3bdca559 add info for WishBone components & unit test 10 years ago
  T. Meissner f0e490142e moved register write into ADDRESS state, decreasing the write to one cycle only 10 years ago
  T. Meissner 285a25132e react to slave ack in ADDRESS state 10 years ago
  T. Meissner 9cac2cb72a add gitignore file 10 years ago
  T. Meissner 500f41f4b7 add init() procedure to t_list_queue type to configure the maximal depth of the linked-list queue 10 years ago
  T. Meissner dfa39921bb add forgotten vhdl2008 dependenciy to queuet target 10 years ago
  T. Meissner ad49871b88 Merge branch 'master' of https://github.com/tmeissner/libvhdl 10 years ago
  T. Meissner 7d60f0ae1b add simple wishbone master and slave with support of classic single write and read as specified in the wishbone spec b4; add unit tests for wishbone m,aster & slave 10 years ago
  T. Meissner b038131ccf add reset value for s_miso in SpiMasterE unit test 10 years ago
  T. Meissner c221b65074 ste is now generated combinatoral in parallel to the fsm 10 years ago
  T. Meissner 8369ba705e add tests for new direction generics/parameters 10 years ago
  T. Meissner 9a38916108 add dir parameter to spi_* procedures to configure direction of data transmission (MSB->LSB and vice versa) 10 years ago
  T. Meissner 5c06158fac add generic G_DATA_DIR to set if we want transfer from LSB to MSB ore vice versa 10 years ago
  T. Meissner 8f2c3f5cd5 printing hex string instead of binary ones in std_logic_vector versions of assert_(un)qual() procedures 10 years ago
  T. Meissner 034b10cdc9 change G_SCLK_DIVIDER range start to 6 (lowest working divider value) and adapt assertion to new range 10 years ago
  T. Meissner 4acbb3c425 using osvvm randompkg to randomize stimuli in SimT tests 10 years ago
  T. Meissner 81ed8e8928 moved deleting of vhdl-2008 packaged from clean to distclean target 10 years ago
  T. Meissner dfa69c148e replaced info about how to get VHDL-2008 packages by info about get_vhdl_2008.sh script 10 years ago
  T. Meissner d8f1bf228c fixed fileendings of VHDL-2008 packages 10 years ago
  T. Meissner 79cc8ce4b3 add script to download VHDL-2008 proposed packages & patch file for env_c.vhdl to get it compiled by GHDL 10 years ago
  T. Meissner 595cee0200 fixed location of vhdl 2008 package files 10 years ago
  T. Meissner db5dfc76b0 fixed broken test for t_list_queue (data width mismatch) 10 years ago
  T. Meissner 78f833a577 add infos about OSVVM library 10 years ago
  T. Meissner 9af05ea4af better comments, add report when wait_cycles() test finished 10 years ago
  T. Meissner 0b3faa2877 using v_count instead of null check for look if queue is empty 10 years ago
  T. Meissner 592893ab2b add version 2.1 of OSVVM library; using osvvm randompkg to randomize stimuli in SpiT tests 10 years ago
  T. Meissner 54168ab07e removed, using string function of VHDL-08 instead 10 years ago
  T. Meissner 3dd69f2d16 fixed stopping of clock when all tests are done 10 years ago
  T. Meissner cd72e16a7e removed forgotten references to deleted StringP.vhd package 10 years ago
  T. Meissner f1de455fd4 fixed wrong period parameter usage in spi_master() procedure 10 years ago
  T. Meissner 76f15e8c76 integrate VHDL-08 libraries 10 years ago
  T. Meissner 74675aa698 removed, using the VHDL-2008 string functions instead 10 years ago
  T. Meissner 5dd42b80a2 add synthesizable and configurable SPI master component and enhance unit test 10 years ago
  T. Meissner dc24fc93b1 fixed reset initialisation of s_sclk_d 10 years ago
  T. Meissner d12f791556 beautify 10 years ago
  T. Meissner 502aec376a replaced direct read from async SpiMosi_i input by read from registered a_mosi 10 years ago
  T. Meissner 308e33cd0c synthesis don't like the std_logic'val(int) construct, change to if/else instead 10 years ago
  T. Meissner 5e7db54e8f add implementation results for SpiSlave component 10 years ago
  T. Meissner a6169f1cdb Merge branch 'master' of https://github.com/tmeissner/libvhdl 10 years ago
  T. Meissner c9fc7388c9 add synthesizable configurable SPI slave component and unit test 10 years ago
  T. Meissner ac5925c717 add synthesizable configurable SPI slave component and unit test 10 years ago
  T. Meissner 2b34512dec clean up assert_* procedures, add new optional parameter for severity level 10 years ago
  T. Meissner 389b3470f1 add cpha parameter do spi_master & spi_slave; change unit test to check all combinations of cpol & cpha 10 years ago
  T. Meissner 10462234cc more and besset comments 10 years ago
  T. Meissner b4e6625524 beautifying 10 years ago
  T. Meissner 61baa0ff9a add information about new AssertP and SimP package components and tests 10 years ago