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cryptocores
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2 Commits (17ce27949ffbb5e743775fb7668c439a2971e052)

Author SHA1 Message Date
  T. Meissner 2d708cbb51 Minor update to TDES sim makefile and testbench 4 years ago
  T. Meissner a2c530928e Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 years ago
  T. Meissner 1d858ce952 added removing of tb_tdes binary and *.o files in clean target 11 years ago
  T. Meissner dd979b5cd3 adapt makefile to new directory structure; new variable SRC_FILES for vhdl sources 12 years ago
  T. Meissner 30a7af4830 moved into seperate vhdl folder 12 years ago
  Torsten Meissner 6c161223d9 moved vhdl testbench files into separate directory vhdl under sim 13 years ago
  Torsten Meissner 114a4e1072 remove OVL support in older, finished & verified projects 13 years ago
  Torsten Meissner b003e5e419 you can now include the OVL library if you set the OVL_ENABLE flag to 1 13 years ago
  Torsten Meissner fbd8c111f5 integrated tcl-file into gtkwave starting parameters 13 years ago
  Torsten Meissner 0feb33c308 extended simulation time to 11 us 13 years ago
  Torsten Meissner b08ff1f872 set assertion level for ghdl to 'error', expanded simulation time to 7us 13 years ago
  Torsten Meissner e1980efa74 longer simulation time 13 years ago
  Torsten Meissner 4b59f1b69d adapted on the initial release of the testbench 13 years ago
  Torsten Meissner cc9989e997 makefile for simulation environment, needs ghdl and gtkwave to work 13 years ago