cryptocores

Author	SHA1	Message	Date
T. Meissner	09da6ae1a6	correct some copy & paste errors in key scheduling process	12 years ago
T. Meissner	734efbc59f	added test cases for decryption in stimuli & checker; bugfix wwith validout detection	12 years ago
T. Meissner	fc78527665	added test data for decryption test cases	12 years ago
T. Meissner	fd799eeed1	change in error message	12 years ago
T. Meissner	4c7037b7c3	added timescale directive and set it to 1 ns/1 ps	12 years ago
T. Meissner	9a340f5524	added timescale directive and set it to 1 ns/1 ps	12 years ago
T. Meissner	bd2f313431	removed 'outdex' reg from waveform viewer	12 years ago
T. Meissner	e40682386a	testbench enhancement * now 2 files with stimuli data: data_input.txt & key_input.txt * new file with the expetcted data output: data_output.txt * new test: Inverse permutation known answer test	12 years ago
T. Meissner	10bcd87d1b	dependency files now moved into 2 variables SRC_FILES & SIM_FILES	12 years ago
T. Meissner	28542ea65b	new verification data files key_input.txt & data_output.txt	12 years ago
T. Meissner	6c9a4f1c2b	stimuli.txt moved to data_input.txt	12 years ago
T. Meissner	ccf8140132	complete refactoring of the des verilog code * now 2 seperate processes: key scheduling & data path * keys are now concurrent wire assignments	12 years ago
T. Meissner	08f7c16e5d	fixed some errors in des helper functions * functions s1() - s8() returned incorrect slices of the matrix * function s2() had one incorrect nibble in cause of faulty conversion	12 years ago
Torsten Meissner	74c974f956	further converting of vhdl into verilog code	13 years ago
Torsten Meissner	5bf2207f11	splitting function ip to 2 sub functions ip0 & ip1	13 years ago
Torsten Meissner	270ac45e53	began with converting of implementation from vhdl to verilog	13 years ago
Torsten Meissner	dd01604dc0	data for stimuli / checker data	13 years ago
Torsten Meissner	9a29954670	new stimuli, checker & reset processes	13 years ago
Torsten Meissner	5fde3ac4a7	added outdex to wave view	13 years ago
Torsten Meissner	5e6c183533	moved vhdl testbench files into separate directory vhdl under sim	13 years ago
Torsten Meissner	3c878ff054	moved vhdl testbench files into separate directory vhdl under sim	13 years ago
Torsten Meissner	3399288adc	change lib path for simulation	13 years ago
Torsten Meissner	6c161223d9	moved vhdl testbench files into separate directory vhdl under sim	13 years ago
Torsten Meissner	8f2e24fb8c	new verilog testbench, makefile & tcl-file	13 years ago
Torsten Meissner	804a359af4	new synchronous process for mode & valid signals	13 years ago
Torsten Meissner	e1900a3e28	all necessary functions are complete now	13 years ago
Torsten Meissner	69c7fe92f9	added functions s1 - s8	13 years ago
Torsten Meissner	c1f59849e5	initial release of des function package in verilog	13 years ago
Torsten Meissner	93186c5d1c	initial release of des verilog implementation, framework code only at the moment	13 years ago
Torsten Meissner	7bfc136dda	Revert "dasdsad" This reverts commit `4b41ea24dd`.	13 years ago
Torsten Meissner	4b41ea24dd	dasdsad	13 years ago
Torsten Meissner	1be72c73b6	Revert "New verily top level file of DES algorithm" This reverts commit `3ff9e3e269`.	13 years ago
Torsten Meissner	3ff9e3e269	New verily top level file of DES algorithm	13 years ago
Torsten Meissner	4f5b5a1830	move vhdl files into separate directories	13 years ago
Torsten Meissner	0b1ef754eb	Revert "move vhdl files into separate directory" This reverts commit `fdc730de69`.	13 years ago
Torsten Meissner	fdc730de69	move vhdl files into separate directory	13 years ago
Torsten Meissner	114a4e1072	remove OVL support in older, finished & verified projects	13 years ago
Torsten Meissner	b003e5e419	you can now include the OVL library if you set the OVL_ENABLE flag to 1 - new variable OVL_ENABLE to enable OVL compile - new variables OVL_LOC & OVL_SRC which point to the OVL library files - new GHDL analyze of the OVL library	13 years ago
Torsten Meissner	fbd8c111f5	integrated tcl-file into gtkwave starting parameters	13 years ago
Torsten Meissner	36aeb55a1c	new tcl-file to control gtkwave	13 years ago
Torsten Meissner	4b8ab0d0cc	added async reset to des-module to avoid simulation warnings and unititialized ports	13 years ago
Torsten Meissner	12bc2b697e	I mean the test vases in NIST document 800-17 ;-)	13 years ago
Torsten Meissner	e32dae12f1	Revision 1.1 2011/09/18 now with all ecb tests of NIST 800-16 publication except the modes-tests	13 years ago
Torsten Meissner	0feb33c308	extended simulation time to 11 us	13 years ago
Torsten Meissner	65aaba575b	initialize all internal variables to 0 to remove numeric_std-lib warnings	13 years ago
Torsten Meissner	ce9571eea6	array signals replaced by constants	13 years ago
Torsten Meissner	a08763c2a0	new test case: Substitution table known answer test - encryption	13 years ago
Torsten Meissner	efacbab6d2	new test case: permutation operation known answer test - encryption	13 years ago
Torsten Meissner	9ff075be14	Revision 1.0.2 2011/09/18 integrated more tests of NIST 800-16 publication	13 years ago
Torsten Meissner	b08ff1f872	set assertion level for ghdl to 'error', expanded simulation time to 7us	13 years ago

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59 Commits (30a7af4830e3ca99ff14e632976c5cf2c82321a8)