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183 Commits (735c411ff8247f1616abf3f4a2214de87dcf62ac)
 

Author SHA1 Message Date
  T. Meissner 716ce2725b moved array type definitions out of functions to head of package, instances now also in package head and are constants 11 years ago
  T. Meissner 45c9409572 more moving of type & constant definitions to pkg header 11 years ago
  T. Meissner 8d0430ac03 moved array type definitions out of functions to head of package, instances now also in package head and are constants 11 years ago
  T. Meissner e9cd57264b changed option 'T' to 'S' 11 years ago
  T. Meissner d3efde1136 added ignore file 11 years ago
  T. Meissner f8226943a3 changed reset & clk timing according to vhdl testbench 11 years ago
  T. Meissner e62c0d5916 added verilog simulation environment 11 years ago
  T. Meissner 3afaaaf4b2 finished conversion of vhdl design into verilog 11 years ago
  Torsten Meißner f7eb3587cf adapted paths 11 years ago
  T. Meissner f76ae71dd3 beauty care 12 years ago
  T. Meissner b6fdf6bbd4 initial commit of cbcdes verilog verification sources 12 years ago
  T. Meissner 7105d21c74 iunitial commit os cbctdes verilog sources 12 years ago
  T. Meissner 67fdd7e63b moved in seperate directory 'vhdl' 12 years ago
  T. Meissner 20f0baca10 moved in seperate directory 'vhdl' 12 years ago
  T. Meissner 0c70ec5653 initial commit of verilog simulation environment for verilog cbcdes core 12 years ago
  T. Meissner 4489748aec initial commit os CBCDES verilog design file 12 years ago
  T. Meissner 51745c47d3 adapt to new directory structure 12 years ago
  T. Meissner 8c33d73411 moved in seperate directory 'vhdl' 12 years ago
  T. Meissner cb76c16c7b moved in seperate directory 'vhdl' 12 years ago
  T. Meissner e8aff41e6e bugfixes to make tdes.v core working correctly 12 years ago
  T. Meissner 5fff1d89d1 initial commit of verilog simulation environment for tdes core 12 years ago
  T. Meissner 553e105986 Merge branch 'master' of https://github.com/tmeissner/cryptocores 12 years ago
  T. Meissner e2225fbbc9 initial commit os TDES verilog design file 12 years ago
  T. Meissner 45403f17d1 import of des verilog design files 12 years ago
  T. Meissner dd979b5cd3 adapt makefile to new directory structure; new variable SRC_FILES for vhdl sources 12 years ago
  T. Meissner 715b8b1229 beauty care 12 years ago
  T. Meissner 30a7af4830 moved into seperate vhdl folder 12 years ago
  T. Meissner 5e422923cf moved into seperate vhdl folder 12 years ago
  T. Meissner d779f5aebe moved into seperate vhdl folder 12 years ago
  T. Meissner 7822728a74 moved into seperate vhdl folder 12 years ago
  T. Meissner c42beff5b8 moved vhdl design files in directory 'vhdl' 12 years ago
  T. Meissner ab47fd3a54 import verilog des design files from des project 12 years ago
  T. Meissner 6356f624af moved vhdl design files in directory 'vhdl' 12 years ago
  T. Meissner 09da6ae1a6 correct some copy & paste errors in key scheduling process 12 years ago
  T. Meissner 734efbc59f added test cases for decryption in stimuli & checker; bugfix wwith validout detection 12 years ago
  T. Meissner fc78527665 added test data for decryption test cases 12 years ago
  T. Meissner bab578f2c6 Merge branch 'master' of https://github.com/tmeissner/cryptocores 12 years ago
  T. Meissner fd799eeed1 change in error message 12 years ago
  T. Meissner 4c7037b7c3 added timescale directive and set it to 1 ns/1 ps 12 years ago
  T. Meissner 9a340f5524 added timescale directive and set it to 1 ns/1 ps 12 years ago
  T. Meissner bd2f313431 removed 'outdex' reg from waveform viewer 12 years ago
  T. Meissner e40682386a testbench enhancement 12 years ago
  T. Meissner 10bcd87d1b dependency files now moved into 2 variables SRC_FILES & SIM_FILES 12 years ago
  T. Meissner 28542ea65b new verification data files key_input.txt & data_output.txt 12 years ago
  T. Meissner 6c9a4f1c2b stimuli.txt moved to data_input.txt 12 years ago
  T. Meissner ccf8140132 complete refactoring of the des verilog code 12 years ago
  T. Meissner 08f7c16e5d fixed some errors in des helper functions 12 years ago
  Torsten Meissner 74c974f956 further converting of vhdl into verilog code 13 years ago
  Torsten Meissner 5bf2207f11 splitting function ip to 2 sub functions ip0 & ip1 13 years ago
  Torsten Meissner 270ac45e53 began with converting of implementation from vhdl to verilog 13 years ago