cryptocores

Author	SHA1	Message	Date
T. Meissner	20f0baca10	moved in seperate directory 'vhdl'	12 years ago
T. Meissner	0c70ec5653	initial commit of verilog simulation environment for verilog cbcdes core	12 years ago
T. Meissner	4489748aec	initial commit os CBCDES verilog design file	12 years ago
T. Meissner	51745c47d3	adapt to new directory structure	12 years ago
T. Meissner	8c33d73411	moved in seperate directory 'vhdl'	12 years ago
T. Meissner	cb76c16c7b	moved in seperate directory 'vhdl'	12 years ago
T. Meissner	e8aff41e6e	bugfixes to make tdes.v core working correctly	12 years ago
T. Meissner	5fff1d89d1	initial commit of verilog simulation environment for tdes core	12 years ago
T. Meissner	553e105986	Merge branch 'master' of https://github.com/tmeissner/cryptocores	12 years ago
T. Meissner	e2225fbbc9	initial commit os TDES verilog design file	12 years ago
T. Meissner	45403f17d1	import of des verilog design files	12 years ago
T. Meissner	dd979b5cd3	adapt makefile to new directory structure; new variable SRC_FILES for vhdl sources	12 years ago
T. Meissner	715b8b1229	beauty care	12 years ago
T. Meissner	30a7af4830	moved into seperate vhdl folder	12 years ago
T. Meissner	5e422923cf	moved into seperate vhdl folder	12 years ago
T. Meissner	d779f5aebe	moved into seperate vhdl folder	12 years ago
T. Meissner	7822728a74	moved into seperate vhdl folder	12 years ago
T. Meissner	c42beff5b8	moved vhdl design files in directory 'vhdl'	12 years ago
T. Meissner	ab47fd3a54	import verilog des design files from des project	12 years ago
T. Meissner	6356f624af	moved vhdl design files in directory 'vhdl'	12 years ago
T. Meissner	09da6ae1a6	correct some copy & paste errors in key scheduling process	12 years ago
T. Meissner	734efbc59f	added test cases for decryption in stimuli & checker; bugfix wwith validout detection	12 years ago
T. Meissner	fc78527665	added test data for decryption test cases	12 years ago
T. Meissner	bab578f2c6	Merge branch 'master' of https://github.com/tmeissner/cryptocores	12 years ago
T. Meissner	fd799eeed1	change in error message	12 years ago
T. Meissner	4c7037b7c3	added timescale directive and set it to 1 ns/1 ps	12 years ago
T. Meissner	9a340f5524	added timescale directive and set it to 1 ns/1 ps	12 years ago
T. Meissner	bd2f313431	removed 'outdex' reg from waveform viewer	12 years ago
T. Meissner	e40682386a	testbench enhancement * now 2 files with stimuli data: data_input.txt & key_input.txt * new file with the expetcted data output: data_output.txt * new test: Inverse permutation known answer test	12 years ago
T. Meissner	10bcd87d1b	dependency files now moved into 2 variables SRC_FILES & SIM_FILES	12 years ago
T. Meissner	28542ea65b	new verification data files key_input.txt & data_output.txt	12 years ago
T. Meissner	6c9a4f1c2b	stimuli.txt moved to data_input.txt	12 years ago
T. Meissner	ccf8140132	complete refactoring of the des verilog code * now 2 seperate processes: key scheduling & data path * keys are now concurrent wire assignments	12 years ago
T. Meissner	08f7c16e5d	fixed some errors in des helper functions * functions s1() - s8() returned incorrect slices of the matrix * function s2() had one incorrect nibble in cause of faulty conversion	12 years ago
Torsten Meissner	74c974f956	further converting of vhdl into verilog code	13 years ago
Torsten Meissner	5bf2207f11	splitting function ip to 2 sub functions ip0 & ip1	13 years ago
Torsten Meissner	270ac45e53	began with converting of implementation from vhdl to verilog	13 years ago
Torsten Meissner	dd01604dc0	data for stimuli / checker data	13 years ago
Torsten Meissner	9a29954670	new stimuli, checker & reset processes	13 years ago
Torsten Meissner	5fde3ac4a7	added outdex to wave view	13 years ago
Torsten Meissner	5e6c183533	moved vhdl testbench files into separate directory vhdl under sim	13 years ago
Torsten Meissner	3c878ff054	moved vhdl testbench files into separate directory vhdl under sim	13 years ago
Torsten Meissner	3399288adc	change lib path for simulation	13 years ago
Torsten Meissner	6c161223d9	moved vhdl testbench files into separate directory vhdl under sim	13 years ago
Torsten Meissner	8f2e24fb8c	new verilog testbench, makefile & tcl-file	13 years ago
Torsten Meissner	804a359af4	new synchronous process for mode & valid signals	13 years ago
Torsten Meissner	e1900a3e28	all necessary functions are complete now	13 years ago
Torsten Meissner	69c7fe92f9	added functions s1 - s8	13 years ago
Torsten Meissner	c1f59849e5	initial release of des function package in verilog	13 years ago
Torsten Meissner	93186c5d1c	initial release of des verilog implementation, framework code only at the moment	13 years ago

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170 Commits (9454ed15cd30f93a794de8d2f0561cab92a7ba2e) All Branches Search

170 Commits (9454ed15cd30f93a794de8d2f0561cab92a7ba2e)

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