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cryptocores
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1 Commits (3de7dd63a953ead42aa834195a62a96cc29abcf1)

Author SHA1 Message Date
  T. Meissner 3de7dd63a9 Add CBC-AES VHDL design & synthesis Makefile 4 years ago
  T. Meissner a2c530928e Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 years ago
  T. Meissner 1850e5c1e3 Add Makefiles for VHDL synthesis of DES & TDES 4 years ago
  T. Meissner 0c70ec5653 initial commit of verilog simulation environment for verilog cbcdes core 12 years ago
  T. Meissner 10bcd87d1b dependency files now moved into 2 variables SRC_FILES & SIM_FILES 12 years ago
  Torsten Meissner 8f2e24fb8c new verilog testbench, makefile & tcl-file 13 years ago
  Torsten Meissner 114a4e1072 remove OVL support in older, finished & verified projects 13 years ago
  Torsten Meissner b003e5e419 you can now include the OVL library if you set the OVL_ENABLE flag to 1 13 years ago
  Torsten Meissner fbd8c111f5 integrated tcl-file into gtkwave starting parameters 13 years ago
  Torsten Meissner 0feb33c308 extended simulation time to 11 us 13 years ago
  Torsten Meissner b08ff1f872 set assertion level for ghdl to 'error', expanded simulation time to 7us 13 years ago
  Torsten Meissner e1980efa74 longer simulation time 13 years ago
  Torsten Meissner 4b59f1b69d adapted on the initial release of the testbench 13 years ago
  Torsten Meissner cc9989e997 makefile for simulation environment, needs ghdl and gtkwave to work 13 years ago