* Optimize setting of valid/data outputs to save
  one cycle
* Replace not working PSL stable assertion by
  seperate helper register and equal compare

* Add some simple PSL checkers & coverage to aes_enc & aes_dec
* Add generating of PSL coverage report
* Add report outputs to testbench

* Split enc & dec in separate units aes_enc & aes_dec
* Add component declarations to aes_pkg
* Key schedule isn't implemented yet
* Fixed round keys at the moment until key schedule is implemented
* Simple test of enc & dec
* New aes top level unit (empty at the moment)
* Renamed makefile to Makefile

* Set VHDL standard to VHDL 2008
* Replace rcon() functuion by simple array constant
* Correct loop range in addroundkey() function

* addroundkey()
* subword()
* rotword()
* rcon()

new generic in aes.vhd: ovl_enable (boolean); copy of aes_pkg.vhd to
integrate ovl functions; copy of tb_aes.vhd to integrate ovl function

move all rtl *.vhd files into the new vhdl directory in the rtl
directory

- OVL now in own library 'accellera_ovl_vhdl
- OVL now default setting
- definition of control OVL configuration record 'ovl_proj_controls' in
package file 'aes_pkg.vhd'