T. Meissner
a2c530928e
Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring
4 years ago
T. Meissner
c5a7007ac5
Implement key schedule for AES decryption, unoptimized
4 years ago
T. Meissner
51d7b485b9
Make PSL compatible with simulation & synthesis
5 years ago
T. Meissner
491b4df54f
Move PSL stuff in generate block; add formal PSL code
5 years ago
T. Meissner
dce8396498
Refactoring; remove unused functions
5 years ago
T. Meissner
50aaca8c6c
Fix PSL cover directives
5 years ago
T. Meissner
28b2cd3856
Implement key schedule for encryption, finally
5 years ago
T. Meissner
77f87536c9
FSM optimizations; PSL enhancements
* Optimize setting of valid/data outputs to save
one cycle
* Replace not working PSL stable assertion by
seperate helper register and equal compare
6 years ago
T. Meissner
c400d2ef1b
Add PSL checkers, refactoring
* Add some simple PSL checkers & coverage to aes_enc & aes_dec
* Add generating of PSL coverage report
* Add report outputs to testbench
6 years ago
T. Meissner
735c411ff8
First working version of AES enc & dec
* Split enc & dec in separate units aes_enc & aes_dec
* Add component declarations to aes_pkg
* Key schedule isn't implemented yet
* Fixed round keys at the moment until key schedule is implemented
* Simple test of enc & dec
* New aes top level unit (empty at the moment)
* Renamed makefile to Makefile
6 years ago
T. Meissner
d8ca919f37
Fixed many incorrect implemented functions
6 years ago
T. Meissner
42a5eb9b1b
Minor refactoring & bugfixing
* Set VHDL standard to VHDL 2008
* Replace rcon() functuion by simple array constant
* Correct loop range in addroundkey() function
6 years ago
T. Meissner
27e06dff2c
Fix gmul() & (inv)mixcolums() functions
6 years ago
T. Meissner
2f91130184
Add remaining AES functions
* addroundkey()
* subword()
* rotword()
* rcon()
9 years ago
T. Meissner
46f1b9295b
merge last changes from amc mini repo
10 years ago
T. Meissner
a83081760f
added prototype of addroundkey() function
11 years ago
T. Meissner
62cd1950fe
add implementation of mixcolumns function
11 years ago
T. Meissner
8a7e15763a
beauty care
11 years ago
T. Meissner
542a5288a4
throw away all ovl stuff
11 years ago
Torsten Meissner
78db757f9d
new verily version of ads, startup code only at the moment
13 years ago
Torsten Meissner
455bcaa289
ovl standard enable, fixed minor bug in pkg
13 years ago
Torsten Meissner
6737c9bf49
partition design in ovl and not ovl enabled
new generic in aes.vhd: ovl_enable (boolean); copy of aes_pkg.vhd to
integrate ovl functions; copy of tb_aes.vhd to integrate ovl function
13 years ago
Torsten Meissner
52cf1fe606
move rtl *.vhd files to the subdirectory vhdl of rtl directory
13 years ago
Torsten Meissner
2e948cf1aa
divide rtl directory in 2 sub-directories: vhdl & verilog
move all rtl *.vhd files into the new vhdl directory in the rtl
directory
13 years ago
Torsten Meissner
4f926c5e88
new function 'mixcolumns'
13 years ago
Torsten Meissner
1cd5fcca51
OVL support further integrated
- OVL now in own library 'accellera_ovl_vhdl
- OVL now default setting
- definition of control OVL configuration record 'ovl_proj_controls' in
package file 'aes_pkg.vhd'
13 years ago
Torsten Meissner
6624df8974
new function invshiftrow
13 years ago
Torsten Meissner
85be1daaf9
correct minor bug
13 years ago
Torsten Meissner
b3dde95682
new primitive function for multiplication in 8 bit galois field
13 years ago
Torsten Meissner
e1c4e19396
filled function shiftrow with functional content
13 years ago
Torsten Meissner
c3026a176f
new function frame shift row, outcommented
13 years ago
Torsten Meissner
00cd0eba79
new function 'sortdata' to put input vector into internal data matrix
13 years ago
Torsten Meissner
25cf2bfb54
new functions: byte sub & invbytesub
13 years ago
Torsten Meissner
4aa2f20b5a
added array constants for forward & reverse s-boxes
13 years ago
Torsten Meissner
42d69ab72f
Initial release, pre-alpha state, only framework code
13 years ago