160 Commits (5ded08aa7bd65242f7d2d102557d88f46149e4ed)
 

Author SHA1 Message Date
  T. Meissner 5ded08aa7b added GPLv2 license file 9 years ago
  T. Meissner 80443e531d internal mode is now a latched copy of mode_i (ITER) 9 years ago
  T. Meissner 034386b0ce removed forgotten data_o drivers from process 9 years ago
  T. Meissner 1e53c62084 data_o is generated in parallel to sync process now 9 years ago
  T. Meissner 5ebdae8b61 add iterative implementation; config via generic 'design_type' 9 years ago
  T. Meissner 1d061d5dc5 Merge branch 'master' of https://github.com/tmeissner/cryptocores 10 years ago
  T. Meissner 579eab1bf0 removed internal synced copy of reset_i; set ready to high in reset 10 years ago
  T. Meissner 1d858ce952 added removing of tb_tdes binary and *.o files in clean target 10 years ago
  T. Meissner a83081760f added prototype of addroundkey() function 10 years ago
  T. Meissner de08e53153 removed internal synced copy of reset_i; set ready to high in reset 10 years ago
  T. Meissner 4b1f3d11f9 removed internal synced copy of reset_i; set ready to high in reset 10 years ago
  T. Meissner a91d55740a wait for rising edge of s_reset before send stimuli data 10 years ago
  T. Meissner 2a2aa23e21 wait for rising edge of reset before send stimuli data 10 years ago
  T. Meissner ad3f36bbec Merge branch 'master' of https://github.com/tmeissner/cryptocores 10 years ago
  T. Meissner 258e9db1e4 removed internal synced copy of reset; set ready to high in reset 10 years ago
  T. Meissner fa93856e07 removed internal synced copy of reset; set ready to high in reset 10 years ago
  T. Meissner dafb56c966 added wait for disactivated reset before running testcases 10 years ago
  T. Meissner 5c74abc86f added wait for disactivated reset before running testcases 10 years ago
  T. Meissner 62cd1950fe add implementation of mixcolumns function 10 years ago
  T. Meissner a51f0ef35b beauty care 10 years ago
  T. Meissner 8a7e15763a beauty care 10 years ago
  T. Meissner daaca1cc94 beauty care 10 years ago
  T. Meissner 5f15362c4a throw away all ovl stuff 10 years ago
  T. Meissner 0a3a1a9769 throw away all ovl stuff 10 years ago
  T. Meissner 542a5288a4 throw away all ovl stuff 10 years ago
  T. Meissner 6c705cf64b moved array type definitions out of functions to head of package, instances now also in package head and are constants 10 years ago
  T. Meissner a89d5ba3d8 moved array type definitions out of functions to head of package, instances now also in package head and are constants 10 years ago
  T. Meissner 716ce2725b moved array type definitions out of functions to head of package, instances now also in package head and are constants 10 years ago
  T. Meissner 45c9409572 more moving of type & constant definitions to pkg header 10 years ago
  T. Meissner 8d0430ac03 moved array type definitions out of functions to head of package, instances now also in package head and are constants 10 years ago
  T. Meissner e9cd57264b changed option 'T' to 'S' 10 years ago
  T. Meissner d3efde1136 added ignore file 10 years ago
  T. Meissner f8226943a3 changed reset & clk timing according to vhdl testbench 10 years ago
  T. Meissner e62c0d5916 added verilog simulation environment 10 years ago
  T. Meissner 3afaaaf4b2 finished conversion of vhdl design into verilog 10 years ago
  Torsten Meißner f7eb3587cf adapted paths 10 years ago
  T. Meissner f76ae71dd3 beauty care 11 years ago
  T. Meissner b6fdf6bbd4 initial commit of cbcdes verilog verification sources 11 years ago
  T. Meissner 7105d21c74 iunitial commit os cbctdes verilog sources 11 years ago
  T. Meissner 67fdd7e63b moved in seperate directory 'vhdl' 11 years ago
  T. Meissner 20f0baca10 moved in seperate directory 'vhdl' 11 years ago
  T. Meissner 0c70ec5653 initial commit of verilog simulation environment for verilog cbcdes core 11 years ago
  T. Meissner 4489748aec initial commit os CBCDES verilog design file 11 years ago
  T. Meissner 51745c47d3 adapt to new directory structure 11 years ago
  T. Meissner 8c33d73411 moved in seperate directory 'vhdl' 11 years ago
  T. Meissner cb76c16c7b moved in seperate directory 'vhdl' 11 years ago
  T. Meissner e8aff41e6e bugfixes to make tdes.v core working correctly 11 years ago
  T. Meissner 5fff1d89d1 initial commit of verilog simulation environment for tdes core 11 years ago
  T. Meissner 553e105986 Merge branch 'master' of https://github.com/tmeissner/cryptocores 11 years ago
  T. Meissner e2225fbbc9 initial commit os TDES verilog design file 11 years ago