T. Meissner - goodcleanfun Gitea

T. Meissner tmeissner

Dresden, Germany
Joined on Oct 22, 2018

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tmeissner pushed to master at tmeissner/formal_hw_verification

db5a7c3c56 Update Link to Tabby CAD suite
cfb36987a2 Link GHA shield badge to GHA workflow
2f06350a33 Fix GHA shield badge
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2 months ago

tmeissner pushed to master at tmeissner/formal_hw_verification

3d29afb13d Modernize Test GHA workflow (#3)

2 months ago

tmeissner pushed to master at tmeissner/cocotb_with_ghdl

51707e3177 Remove files added by mistake
dd32a55377 Better hex conversion
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3 months ago

tmeissner pushed to master at tmeissner/cocotb_with_ghdl

eecdbafe83 Also clean in cleanall target
ee82cb5f44 Add .ruff_cache and __pycache__ to gitignore
afc12ee9d0 Fix target order
a370bfa701 Code reformatted by ruff
ec50ef00fa Replace * imports by selective ones
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3 months ago

tmeissner pushed to master at tmeissner/cocotb_with_ghdl

f7d6238731 Add AES test which uses pyuvm

3 months ago

tmeissner pushed to master at tmeissner/cocotb_with_ghdl

86b76548e8 Add support to use NVC for simulation
80fb3ed2bb Add pyuvm as git submodule
4a0c9dc42b Merge pull request #1 from cmarqu/patch-1
6609bfecc9 Typofixes
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4 months ago

tmeissner pushed to main at tmeissner/gatemate_experiments

5d9943c78f Remove CC_CTRL_END component, use CC_USR_RSTN instead

5 months ago

tmeissner pushed to master at tmeissner/openscad

edc93ea613 Add tubeless ventil adapter

1 year ago

tmeissner pushed to master at tmeissner/Dockerfiles

0cfec66ecb Update link to Yosys docs

1 year ago

tmeissner pushed to master at tmeissner/Dockerfiles

dbd318c85d Add icarus verilog to gatemate docker image

1 year ago

tmeissner pushed to main at tmeissner/gatemate_experiments

bb98b0e5f5 Add comments with some hints to yosys & p_r options and their effects
9c353f3446 Remove unused local neorv32_top; adapt neorv32_aes top-level
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1 year ago

tmeissner pushed to master at tmeissner/psl_with_ghdl

00b124e266 Add issue code for ghdl/ghdl#2336

1 year ago

tmeissner pushed to main at tmeissner/gatemate_experiments

6b1b376932 Use speed instead of moderate FPGA speed grade

1 year ago

tmeissner pushed to main at tmeissner/gatemate_experiments

e845a0d530 Bring back neorv32_aes.vhd, which was wrongly deleted

1 year ago

tmeissner pushed to main at tmeissner/gatemate_experiments

d982691506 Update neorv32 submodule
3ae59c3b5c Use neorv-repo top level instead of local one
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1 year ago

tmeissner pushed to main at tmeissner/gatemate_experiments

bf6508d941 Add info about neorv32_aes and uart_aes to README

1 year ago

tmeissner pushed to main at tmeissner/gatemate_experiments

89730f767a Use random stimuli in uart_loop testbench
1777fbd742 Add uart_aes design, simulation & fpga-flow
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1 year ago

tmeissner pushed to main at tmeissner/gatemate_experiments

f8ba0b17c2 Add VHDL sim for RTL & Verilog sim for post-syn simulation
b8d7ecd701 Update neorv32_aes top level; Add some iverilog options
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1 year ago

tmeissner pushed to main at tmeissner/gatemate_experiments

84f2515433 Update neorv32 submodule

1 year ago

tmeissner pushed to main at tmeissner/gatemate_experiments

b01669c135 Update Makefile to build cryptocores AES-CTR component
194f4c78e0 Update neorv32 submodule
ab480c6fab Remove old neorv32 top level, neorv32_aes is used instead now
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1 year ago