 T. Meissner
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67df839c95
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add implementation & testbench of CBCMAC with DES algorithm
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10 years ago |
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T. Meissner
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393757693e
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add removing of testbench binary to clean target
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10 years ago |
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T. Meissner
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82ae83f1dc
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adapted to ITER & PIPE configuration, supports now both settings
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10 years ago |
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T. Meissner
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af8fe6023d
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add accept signals to waveform view
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10 years ago |
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T. Meissner
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cfd20a9bbc
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add removing of object files to clean target
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10 years ago |
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T. Meissner
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5ded08aa7b
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added GPLv2 license file
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10 years ago |
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T. Meissner
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80443e531d
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internal mode is now a latched copy of mode_i (ITER)
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10 years ago |
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T. Meissner
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034386b0ce
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removed forgotten data_o drivers from process
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10 years ago |
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T. Meissner
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1e53c62084
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data_o is generated in parallel to sync process now
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10 years ago |
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T. Meissner
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5ebdae8b61
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add iterative implementation; config via generic 'design_type'
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10 years ago |
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T. Meissner
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1d061d5dc5
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Merge branch 'master' of https://github.com/tmeissner/cryptocores
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11 years ago |
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T. Meissner
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579eab1bf0
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removed internal synced copy of reset_i; set ready to high in reset
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11 years ago |
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T. Meissner
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1d858ce952
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added removing of tb_tdes binary and *.o files in clean target
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11 years ago |
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T. Meissner
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a83081760f
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added prototype of addroundkey() function
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11 years ago |
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T. Meissner
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de08e53153
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removed internal synced copy of reset_i; set ready to high in reset
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11 years ago |
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T. Meissner
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4b1f3d11f9
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removed internal synced copy of reset_i; set ready to high in reset
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11 years ago |
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T. Meissner
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a91d55740a
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wait for rising edge of s_reset before send stimuli data
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11 years ago |
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T. Meissner
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2a2aa23e21
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wait for rising edge of reset before send stimuli data
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11 years ago |
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T. Meissner
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ad3f36bbec
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Merge branch 'master' of https://github.com/tmeissner/cryptocores
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11 years ago |
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T. Meissner
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258e9db1e4
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removed internal synced copy of reset; set ready to high in reset
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11 years ago |
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T. Meissner
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fa93856e07
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removed internal synced copy of reset; set ready to high in reset
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11 years ago |
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T. Meissner
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dafb56c966
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added wait for disactivated reset before running testcases
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11 years ago |
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T. Meissner
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5c74abc86f
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added wait for disactivated reset before running testcases
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11 years ago |
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T. Meissner
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62cd1950fe
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add implementation of mixcolumns function
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11 years ago |
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T. Meissner
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a51f0ef35b
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beauty care
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11 years ago |
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T. Meissner
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8a7e15763a
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beauty care
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11 years ago |
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T. Meissner
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daaca1cc94
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beauty care
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11 years ago |
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T. Meissner
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5f15362c4a
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throw away all ovl stuff
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11 years ago |
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T. Meissner
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0a3a1a9769
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throw away all ovl stuff
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11 years ago |
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T. Meissner
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542a5288a4
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throw away all ovl stuff
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11 years ago |
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T. Meissner
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6c705cf64b
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moved array type definitions out of functions to head of package, instances now also in package head and are constants
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11 years ago |
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T. Meissner
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a89d5ba3d8
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moved array type definitions out of functions to head of package, instances now also in package head and are constants
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11 years ago |
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T. Meissner
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716ce2725b
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moved array type definitions out of functions to head of package, instances now also in package head and are constants
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11 years ago |
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T. Meissner
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45c9409572
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more moving of type & constant definitions to pkg header
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11 years ago |
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T. Meissner
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8d0430ac03
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moved array type definitions out of functions to head of package, instances now also in package head and are constants
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11 years ago |
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T. Meissner
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e9cd57264b
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changed option 'T' to 'S'
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11 years ago |
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T. Meissner
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d3efde1136
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added ignore file
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11 years ago |
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T. Meissner
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f8226943a3
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changed reset & clk timing according to vhdl testbench
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11 years ago |
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T. Meissner
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e62c0d5916
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added verilog simulation environment
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11 years ago |
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T. Meissner
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3afaaaf4b2
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finished conversion of vhdl design into verilog
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11 years ago |
 Torsten Meißner
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f7eb3587cf
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adapted paths
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11 years ago |
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T. Meissner
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f76ae71dd3
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beauty care
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12 years ago |
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T. Meissner
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b6fdf6bbd4
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initial commit of cbcdes verilog verification sources
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12 years ago |
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T. Meissner
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7105d21c74
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iunitial commit os cbctdes verilog sources
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12 years ago |
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T. Meissner
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67fdd7e63b
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moved in seperate directory 'vhdl'
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12 years ago |
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T. Meissner
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20f0baca10
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moved in seperate directory 'vhdl'
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12 years ago |
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T. Meissner
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0c70ec5653
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initial commit of verilog simulation environment for verilog cbcdes core
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12 years ago |
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T. Meissner
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4489748aec
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initial commit os CBCDES verilog design file
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12 years ago |
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T. Meissner
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51745c47d3
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adapt to new directory structure
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12 years ago |
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T. Meissner
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8c33d73411
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moved in seperate directory 'vhdl'
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12 years ago |
