cryptocores

Author	SHA1	Message	Date
T. Meissner	a2c530928e	Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring	4 years ago
T. Meissner	1850e5c1e3	Add Makefiles for VHDL synthesis of DES & TDES	4 years ago
T. Meissner	46f1b9295b	merge last changes from amc mini repo	10 years ago
T. Meissner	8a9b30940e	integrate s1-s8() into one s() function with additional parameter s_table; convert lower to upper case	10 years ago
T. Meissner	8f575798ea	add .PHONY to clean target	10 years ago
T. Meissner	3531c69ce1	add support for ITER & PIPE variations of DES verilog implementation	10 years ago
T. Meissner	9454ed15cd	removed assignments of c & d in r & l process reset state	10 years ago
T. Meissner	6dd9c4ad6c	removed wrong assignments of r in the c & d process	10 years ago
T. Meissner	cb14f089b9	add acceptin & acceptout ports	10 years ago
T. Meissner	b9efb85f01	add second iterative implementation; selection between the two implementations by #ifdef's	10 years ago
T. Meissner	393757693e	add removing of testbench binary to clean target	10 years ago
T. Meissner	82ae83f1dc	adapted to ITER & PIPE configuration, supports now both settings	10 years ago
T. Meissner	af8fe6023d	add accept signals to waveform view	10 years ago
T. Meissner	cfd20a9bbc	add removing of object files to clean target	10 years ago
T. Meissner	80443e531d	internal mode is now a latched copy of mode_i (ITER)	10 years ago
T. Meissner	034386b0ce	removed forgotten data_o drivers from process	10 years ago
T. Meissner	1e53c62084	data_o is generated in parallel to sync process now	10 years ago
T. Meissner	5ebdae8b61	add iterative implementation; config via generic 'design_type'	10 years ago
T. Meissner	a51f0ef35b	beauty care	11 years ago
T. Meissner	45c9409572	more moving of type & constant definitions to pkg header	11 years ago
T. Meissner	8d0430ac03	moved array type definitions out of functions to head of package, instances now also in package head and are constants	11 years ago
T. Meissner	e9cd57264b	changed option 'T' to 'S'	11 years ago
T. Meissner	09da6ae1a6	correct some copy & paste errors in key scheduling process	12 years ago
T. Meissner	734efbc59f	added test cases for decryption in stimuli & checker; bugfix wwith validout detection	12 years ago
T. Meissner	fc78527665	added test data for decryption test cases	12 years ago
T. Meissner	fd799eeed1	change in error message	12 years ago
T. Meissner	4c7037b7c3	added timescale directive and set it to 1 ns/1 ps	12 years ago
T. Meissner	9a340f5524	added timescale directive and set it to 1 ns/1 ps	12 years ago
T. Meissner	bd2f313431	removed 'outdex' reg from waveform viewer	12 years ago
T. Meissner	e40682386a	testbench enhancement * now 2 files with stimuli data: data_input.txt & key_input.txt * new file with the expetcted data output: data_output.txt * new test: Inverse permutation known answer test	12 years ago
T. Meissner	10bcd87d1b	dependency files now moved into 2 variables SRC_FILES & SIM_FILES	12 years ago
T. Meissner	28542ea65b	new verification data files key_input.txt & data_output.txt	12 years ago
T. Meissner	6c9a4f1c2b	stimuli.txt moved to data_input.txt	12 years ago
T. Meissner	ccf8140132	complete refactoring of the des verilog code * now 2 seperate processes: key scheduling & data path * keys are now concurrent wire assignments	12 years ago
T. Meissner	08f7c16e5d	fixed some errors in des helper functions * functions s1() - s8() returned incorrect slices of the matrix * function s2() had one incorrect nibble in cause of faulty conversion	12 years ago
Torsten Meissner	74c974f956	further converting of vhdl into verilog code	13 years ago
Torsten Meissner	5bf2207f11	splitting function ip to 2 sub functions ip0 & ip1	13 years ago
Torsten Meissner	270ac45e53	began with converting of implementation from vhdl to verilog	13 years ago
Torsten Meissner	dd01604dc0	data for stimuli / checker data	13 years ago
Torsten Meissner	9a29954670	new stimuli, checker & reset processes	13 years ago
Torsten Meissner	5fde3ac4a7	added outdex to wave view	13 years ago
Torsten Meissner	5e6c183533	moved vhdl testbench files into separate directory vhdl under sim	13 years ago
Torsten Meissner	3c878ff054	moved vhdl testbench files into separate directory vhdl under sim	13 years ago
Torsten Meissner	3399288adc	change lib path for simulation	13 years ago
Torsten Meissner	6c161223d9	moved vhdl testbench files into separate directory vhdl under sim	13 years ago
Torsten Meissner	8f2e24fb8c	new verilog testbench, makefile & tcl-file	13 years ago
Torsten Meissner	804a359af4	new synchronous process for mode & valid signals	13 years ago
Torsten Meissner	e1900a3e28	all necessary functions are complete now	13 years ago
Torsten Meissner	69c7fe92f9	added functions s1 - s8	13 years ago
Torsten Meissner	c1f59849e5	initial release of des function package in verilog	13 years ago

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81 Commits (d7b39f322e4d4e8f9feed20d6d92c01a658cc757)